Verilog

Bracket

Bracket style

• Ansi

  A1

  initial
  begin
      areg = 0;
  end

• KR

  A2

  initial begin
      areg = 0;
  end

• GNU

  A3

  initial
    begin
      areg = 0;
    end

• None

Indentation

Indent using

• Spaces

  s

  initial
  begin
  ****$display("a=%h*b=%d",
  *************rval,
  *************rval);
  end

• Tab

  t

  initial
  begin
  --->$display("a=%h*b=%d",
  --->*********rval,
  --->*********rval);
  end

• Force tab

  T

  initial
  begin
  --->$display("a=%h*b=%d",
  --->--->--->*rval,
  --->--->--->*rval);
  end

Indent number

• Range : 2-20

  *Attach to previous short

  //indent_number4
  initial
  begin
      areg = 0;
  end
  
  //indent_number5
  initial
  begin
       areg = 0;
  end

Indent brackets

• Yes

  B

  initial
      begin
      areg = 0;
      end

• No

  initial
  begin
      areg = 0;
  end

Indent blocks

• Yes

  G

  initial
      begin
          areg = 0;
      end

• No

  initial
  begin
      areg = 0;
  end

Min conditional indent

• Range : 0-20

  m

  //min-conditional-indent0
  if (a > b
      || c > d)
      out1 <= int1;
  
  //min-conditional-indent6
  if (a > b
        || c > d)
      out1 <= int1;

Max instatement indent

• Range : 40-120

  M

  fooFunction(barArg1,
           barArg2,
           barArg3);
  
  becomes (with larger value)
  
  fooFunction(barArg1,
              barArg2,
              barArg3);

Fill empty lines

• Yes

  E

  initial
  begin
  ****areg*=*0;
  ****
  ****areg*=*1;
  end

• No

  initial
  begin
  ****areg*=*0;
  
  ****areg*=*1;
  end

Indent preprocessor

• Yes

  w

  `define aa \
          a + b

• No

  `define aa \
  a + b

Formatting

Brackets break

• Yes

  b

  // ANSI
  initial
  begin
      areg = 0;
  end

• No

Brackets attach

• Yes

  a

  // KR
  initial begin
      areg = 0;
  end

• No

Keep one line statements

• Yes

  o

  initial
  begin
      areg = 0;areg = 1;
  end
  
  //remains unchanged.

• No

  initial
  begin
      areg = 0;
      areg = 1;
  end

Keep one line blocks

• Yes

  O

  initial
  begin
      areg = 0;areg = 1;
  end
  
  //remains unchanged.

• No

  initial
  begin
      areg = 0;
      areg = 1;
  end

Pad operators

• Yes

  p

  if (a > b)
      out1 <= int1;

• No

  if (a>b)
      out1<=int1;

Pad parens

• Yes

  L

  if ( isFoo( a, b ) )
      bar( a, b );

• No

  if (isFoo(a, b))
      bar(a, b);

Pad block

• Yes

  l

  if (isFoo(a, b))
  begin bar(a, b);
  end

• No

  if (isFoo(a, b))
      bar(a, b);

Pad all

• Yes

  P

  if ( isFoo( a, b ) )
  begin bar( a, b );
  end

• No

  if (isFoo(a, b))
      bar(a, b);

Convert tabs

• Yes

  c

  initial
  begin
  ****areg****=*0;
  end

• No

  initial
  begin
  ****areg--->=*0;
  end

Break blocks

• Yes

  f

  initial
  begin
      areg = 0;
  
      if (a > b)
      begin
          areg = 1;
      end
  
      areg = 2;
  end

• No

  initial
  begin
      areg = 0;
      if (a > b)
      begin
          areg = 1;
      end
      areg = 2;
  end

Break all blocks

• Yes

  F

  initial
  begin
      areg = 0;
  
      if (a > b)
      begin
          areg = 1;
      end
  
      else if (a < b)
      begin
          areg = 1;
      end
  
      areg = 2;
  end

• No

  initial
  begin
      areg = 0;
      if (a > b)
      begin
          areg = 1;
      end
      else if (a < b)
      begin
          areg = 1;
      end
      areg = 2;
  end

Break elseifs

• Yes

  e

  initial
  begin
      if (a > b)
      begin
          areg = 1;
      end
      else
          if (a < b)
          begin
              areg = 1;
          end
  end

• No

  initial
  begin
      if (a > b)
      begin
          areg = 1;
      end
      else if (a < b)
      begin
          areg = 1;
      end
  end